1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming improved transistors that have improved high frequency response.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device performance requirements in integrated circuits. To facilitate the increase in circuit functionality, new technologies are constantly needed to increase the performance of the semiconductor devices. This improvement in device performance may involve higher frequency performance as well as increased frequency performance at low current densities which enables low power circuit designs. However, a successful technology must provide high performance with increased circuit performance at low wafer cost.
Transistor performance is of particular concern in bipolar transistor design. Bipolar transistors are commonly used for analog devices where operational speed is of paramount concern. There are many different critical features in the design of high performance bipolar transistors. These include the intrinsic and extrinsic base resistance, the vertical profile of the base doping and germanium fraction, the collector doping, collector-base and base-emitter capacitances, and collector and emitter resistances. To achieve higher power performance, it is generally desirable to reduce intrinsic and extrinsic base resistence. Reducing the base resistence increases the maximum operating frequency (fmax) of the transistor. Unfortunately, most methods to reduce base resistence are hampered by: 1) implantation enhanced diffusion of the intrinsic base dopant caused by the implantation process for the extrinsic base which widens the intrinsic base and thus reduces its frequency performance; 2) high wafer cost caused by a complex transistor process; and 3) difficulty of integrating the NPN device process with the CMOS process steps.
Thus, what is needed is an improved device structure and method that improves transistor performance with minimal cost and process complexity. Without an improved method and structure for forming such devices the performance of these devices will continue to be compromised.